Bring RISC-V to your course in computer architecture using RVfpga
This in-person workshop shows you how to use RISC-V to teach computer architecture and the design of systems on chip (SoCs). Give us a day of your time and you will be able to empower the next generation computer science, electrical and computer engineering students to get hands-on expertise in computer architecture and the RISC-V instruction set architecture.
What will you learn?
The workshop shows how to quickly get the RISC-V FPGA system and RISC-V tools up and running. Then, we describe all of the RVfpga labs and show how to use and work through a selection of the labs hands-on. We also discuss how to integrate RVfpga into your curriculum.
Specific topics include:
- Installing tools (which can be done before the workshop)
- Targeting the SweRV EH1 RISC-V core and SoC to an FPGA
- Programming the RISC-V SoC
- Adding functionality to the RISC-V SoC
- Analyzing and modifying the RISC-V-core and memory hierarchy
Date: 7th March and 8th March (follow hyperlink to register for this date)
Time: 09:00 to 17:00 (GMT +9)
Location: Daikaigisitu(大会議室), 3rd floor, Building 16-a, Yagami campus, Keio University, 3 Chome-14-1 Hiyoshi, Kohoku Ward Yokohama, Kanagawa, 223-8522 Japan