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	New User Requesting Help By Dawgburt 4 days ago \| Last Post: 2 hours ago	RVfpga: Understanding Computer Architecture & Introduction to SoC
	Hi @dawgburt, I'm also having problems with the ... 2 hours ago By dchav... This is the terminal output when I launch VSCode -... 2 days ago By Dawgb... I tried editing it a 2nd time but it seems it didn... 2 days ago By Dawgb... Thank you, this helped. I had an error in the envi... 2 days ago By Dawgb... Hi again, I've been testing Catapult v2024.1.2 i... 2 days ago By dchav... Ok. Later today I'll compare your Configure Platfo... 2 days ago By dchav... Here is a screen shot of my Catapult Configure Pla... 3 days ago By Dawgb... @dchaver I followed 5.A exactly, for Blinky as my ... 3 days ago By Dawgb... Hello, I've just tried in my Windows machine (wh... 3 days ago By dchav... Hello,I am a new user. I am doing independent lear... 4 days ago By Dawgb... view all posts
	How do I use RISC-V FPGA in the other board instead "Nexys A7" board? By taeyeong 3 years ago \| Last Post: 8 hours ago	RVfpga: Understanding Computer Architecture & Introduction to SoC
	Hi, In v3.0 we added support for some more board... 8 hours ago By dchav... @dchaver It seems that it's not just about modif... 2 days ago By plc33... Hi @plc330, Sorry for my late replay, I've just ... 3 months ago By dchav... Can I use the digilent genesys2 FPGA board to comp... 4 months ago By plc33... Hi.@dchaver 可以正常工作了。 🤗 非常感谢。 It works.... 2 years ago By Mattt... hi.@dchaver I can't open the website, can you s... 2 years ago By Mattt... Hi @matttttt, I've been doing several tests. I t... 2 years ago By dchav... @dchaver 我重新上传附件总是失败，这是什么原因啊？ 2 years ago By Mattt... @matttttt , I cannot find any attachment in your p... 2 years ago By dchav... hi.@dchaver 我使用的是RVfpga1.0。我测试了其他的例子，它们和VectorS... 2 years ago By Mattt... Hi @matttttt, - In RVfpga v1.1, the VectorSortin... 2 years ago By dchav... Dear rcwo. I use the NEXYS4(WITHOUT DDR) instea... 2 years ago By Mattt... @richard-alexander-5 It's not big enough. You need... 2 years ago By RCWO @rcwo Thanks for the answer. I have a spartan 6 to... 2 years ago By Richa... @richard-alexander-5 The current configurations of... 2 years ago By RCWO @rcwo Greetings. I'm learning RISC-V and I have a ... 2 years ago By Richa... Dear Taeyong. The ZCU-106 is a very big and expens... 3 years ago By RCWO I want to use "zcu-106" board instead "Nexys A7" b... 3 years ago By taeye... view all posts
	RVfpgaSOC Lab5 cmake error By plc330 1 day ago \| Last Post: 8 hours ago	RVfpga: Understanding Computer Architecture & Introduction to SoC
	Hi, Did you check out the exact versions specifi... 8 hours ago By Zubai... I encountered the following issue while working on... 1 day ago By plc33... view all posts
	Lab 18 - Vivado Synthesis error: module 'adder' not found By AlfonsoMC 1 week ago \| Last Post: 1 week ago	RVfpga: Understanding Computer Architecture & Introduction to SoC
	@dchaver Hello, I have managed to fix the pro... 1 week ago By Alfon... Hello Alfonso, First of all, let me ask you some... 1 week ago By dchav... I am trying to generate the bitstream in Vivado in... 1 week ago By Alfon... view all posts
	Lab18 empty espresso.exe output on Windows 10 By michalmonday 2 years ago \| Last Post: 4 weeks ago	RVfpga: Understanding Computer Architecture & Introduction to SoC
	Hi, In windows you should use the espresso.exe f... 4 weeks ago By dchav... @dchaver Hello, I have an error in cygwin when ... 4 weeks ago By delet... Yes Michal, you are right: t3 and t4 should be swa... 2 years ago By dchav... Thank you very much, using Cygwin fixes the proble... 2 years ago By micha... File "MyTest_Windows10_Cygwin.txt" MyTest_... 2 years ago By dchav... Dear Michal, I've just replicated the process th... 2 years ago By dchav... Hello, I'm trying to follow the Lab18 script on Wi... 2 years ago By micha... view all posts

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