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Lab 1 error with Vivado 2021.1 on Manjaro

 

JiaChen
(@jiachen)
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Joined: 1 year ago
Posts: 2
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Hi, I followed all the lab instruction steps in lab 1 but failed to generate a bitstream.

3 errors existed.

[HDL 9-3952] use of undefined macro 'AXI_TYPEDEF_AW_CHAN_T' ["/home/kaminari/RVFPGA/RVfpga/src/SweRVolfSoC/Interconnect/AxiInterconnect/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv":402]

[Synth 8-1717] cannot access memory enable directly ["/home/kaminari/RVFPGA/RVfpga/src/SweRVolfSoC/Peripherals/SystemController/swervolf_syscon.v":337]


   
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JiaChen
(@jiachen)
New Member
Joined: 1 year ago
Posts: 2
Topic starter  

Problem solved. Set swervolf_syscon.v to be sv file tyoe


   
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