Hi!
I have collected some data using SweRVolfSoC. I want to filter the data using fir filter. In fact, it is to perform multiplication and addition operations on these data. If you use software algorithms for filtering, it may consume a lot of clock cycles. In order to reduce the consumption of clock cyclesso, so I wonder if I can define an instruction specifically for filtering. Since there is no introduction on how to expand the instructions in the lab, I don't know if it is feasible to do so. Another method is to build a fir filter of wishborn bus, and then hook it to the soc bus, but I did not find a peripheral with this structure. I want to know which of these two methods is more feasible and how to do with it.
Dear @my123,
This is a very important topic!
One of the key aspects to RISC-V is the provision of the same small instruction set for all processors along with the ability to build groups of specialised instructions oriented towards specific applications. This is fundamental to driving growth in the use of RISC-V processors.
So, this will be a topic that we will address in detail in expanded materials due later this year (likely in October).
I asked one of our Authors, Prof. Daniel Chaver-Martinez to give his thoughts on this:
In RVfpga v2.0 we will explain in detail how the different types of instructions execute through the SweRV EH1 processor and then we will include a whole lab with descriptions and exercises on how to add new instructions to the core (for example, we will show how to add bit-manipulation and floating-point instructions).
To illustrate the steps, if you want to include new arithmetic-logic instructions, you must modify the following modules/files:
- File swerv_types.sv [swerv_types.sv]: It includes several structures that group together the control signals related with the different parts of the processor. Specifically, two structures are mainly used for controlling the execution of arithmetic-logic instructions: structure dec_pkt_t and structure alu_pkt_t.
- Module dec_decode_ctl: The instruction is decoded in this module and the control signals for its execution are generated. Note that, for example, signals i0_ap and i0_ap, of type alu_pkt_t, are defined here. You will have to modify/add some signals related with your new instructions. In lines 2482-2495 it is explained how to generate all the equations using open-source tools. You can do it this way or manually by modifying/adding the specific control signals related with your instructions.
- Module exu: The arithmetic-logic instructions are executed here. Note that the ALUs (exu_alu_ctl), the pipelined Multiplier (exu_mul_ctl) and the non-pipelined Divider (exu_div_ctl) are instantiated in module exu.
- Take into account that if you introduce new mnemonics not supported by the assembler, you will have to write the new instructions directly in machine code in your assembly program.
The method of building a FIR Filter and hook it to the SoC Bus looks feasible but you will need to find a proper peripheral."
We hope this is helpful and promise you that much more is coming on this vital topic!
Our best to you,
Robert Owen
Dear @rcwo
First of all, thank you very much for your detailed answer. I also think it is a wise choice to connect the FIR filter with Wishbone structure to the bus. However, I couldn't find any filters for this structure on Opencores. What other sites offered IP cores that I could use for free?
Dear @my123
That's about all we can advise at this stage. More follows later this year.
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