RVfpga – Introduction to RVfpgaSoC – traditional Chinese – V1.0
Version 1.0 (first release): 16th July 2021
The original release of the RVfpga SoC Design course.
This RVfpga-SoC course shows how to build a RISC-V SoC from scratch using provided building blocks and a visual block-based design approach.
The building blocks include the SweRV EH 1 CPU core, Interconnect, Boot-ROM, System controller, and GPIO controller. The SoC created by the user using the block design approach is a subset of SweRVolfX. Subsequent labs show how to run programs on the SoC, compare the block design SoC with SweRVolf made using FuseSoC, run Zephyr real-time operating system on SweRVolf, and then run a Tensorflow Lite Hello-World example on SweRVolf.
The following labs are provided:
- Lab 1: Introduction to RVfpga-SoC
- Lab 2: Running Software on RVfpga-SoC
- Lab 3: Introduction to SweRVolf and FuseSoC
- Lab 4: Running Zephyr on SweRVolf
- Lab 5: Running Tensorflow Lite on SweRVolf
These labs show how to create an SoC from a core and other building blocks (Lab 1), how to target it to an FPGA and run programs on the newly created SoC (Labs 2), how to use a FuseSoC-based SoC (SweRVolf) for SweRV EH1 (Labs 3), how to add a real-time operating system (RTOS) to SweRVolf (Lab 4). and how to run Tensorflow Lite’s Hello World example on SweRVolf (Lab 5).