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RVfpga- Understanding Computer Architecture Simplified Chinese Version V2.0

Version 2.0

Simplified Chinese Version 1.0 (first release): 1st April 2020 


The original release of the RVfpga course.

o   Original release of the RVfpga course.

o   Included Getting Started Guide and Labs 0-10


Simplified Chinese Version 2.0: 9th May 2022


o Added Labs 11-20: documents, figures, software sources, exercises, and solutions. Labs 11-20 focus on microarchitecture and memory hierarchy. They show how to use the performance counters available in the SweRV EH1 processor, how to understand the SweRV EH1 pipeline, including how basic instructions (arithmetic-logic, memory, branch) are executed and how structural, data and control hazards are handled, and how to use or add features to the RISC-V core, including adding additional instructions and performance counters, using the branch predictors, and exploring memory features.

o Extended the slides to cover the new labs.

o Added some minor text/figures in the GSG and Labs 0-10 and fixed some typos.

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o 增加了实验室11-20:文件、数字、软件来源、练习和解决方案。实验室11-20的重点是微架构和内存层次结构。它们展示了如何使用SweRV EH1处理器中可用的性能计数器,如何理解SweRV EH1流水线,包括如何执行基本指令(算术-逻辑、内存、分支)以及如何处理结构、数据和控制危险,以及如何使用或增加RISC-V内核的功能,包括增加额外的指令和性能计数器,使用分支预测器,以及探索内存功能。

o 扩展了幻灯片,以涵盖新的实验内容。

o 在GSG和0-10实验室中增加了一些小的文字/图片,并修正了一些错别字。