RVfpga: Understanding Computer Architecture RVfpga_V2.2_ENG
Version 1.0 (first release): 30th November 2020
The original release of the RVfpga course.
o Original release of the RVfpga course.
o Included Getting Started Guide and Labs 0-10
Version 1.1 : 8th June 2021
o Added description of Labs 11-20 in Lab 0.
o Updated SweRVolf version to 0.7.3 and Verilator version to 4.106.
o Added Boot ROM initialization program.
o Added new Figure 1 and Table 1 in the GSG describing the RVfpga System
o Added a UART exercise to Lab 10.
o Fixed some typos.
Version 2.0 : 3rd Dec 2021
o Added Labs 11-20: documents, figures, software sources, exercises, and solutions. Labs 11-20 focus on microarchitecture and memory hierarchy. They show how to use the performance counters available in the SweRV EH1 processor, how to understand the SweRV EH1 pipeline, including how basic instructions (arithmetic-logic, memory, branch) are executed and how structural, data and control hazards are handled, and how to use or add features to the RISC-V core, including adding additional instructions and performance counters, using the branch predictors, and exploring memory features.
o Extended the slides to cover the new labs.
o Added some minor text/figures in the GSG and Labs 0-10 and fixed some typos.
Version 2.1 : 7th Feb 2022
o Renumbered Labs 1-5: moved Lab 1 to Lab 5 and renumbered Labs 2-5 as 1-4.
Version 2.2 : 3th May 2022
The revision to include the workshop materials makes three main changes:
* Removes Lab 0 (most of this material is moved to the ReadmeFirst.docx document).
* Creates a ReadmeFirst.docx document – which enables ease of use for everyone.
* Adds a Workshop_Guide.docx document.
We also factored all the documents (GSG, slides, the IUP brochure, license agreement, and workshop guide) into a Documents folder.