RVfpga- Understanding Computer Architecture Traditional Chinese Version_V2.0
Traditional Chinese Version 1.0: 9th April 2020
Traditional Chinese Version 2.0: 23rd May 2022
o Added Labs 11-20: documents, figures, software sources, exercises, and solutions. Labs 11-20 focus on microarchitecture and memory hierarchy. They show how to use the performance counters available in the SweRV EH1 processor, how to understand the SweRV EH1 pipeline, including how basic instructions (arithmetic-logic, memory, branch) are executed and how structural, data and control hazards are handled, and how to use or add features to the RISC-V core, including adding additional instructions and performance counters, using the branch predictors, and exploring memory features.
o Extended the slides to cover the new labs.
o Added some minor text/figures in the GSG and Labs 0-10 and fixed some typos.
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