RVfpga: Understanding Computer Architecture – v1.1
Version 1.0 (first release): 30th November 2020
The original release of the RVfpga course.
Version 1.1 : 8th June 2021
o Added description of Labs 11-20 in Lab 00.
o Updated SweRVolf version to 0.7.3.
o Updated Verilator version to 4.106.
o Added Boot ROM initialization program.
o Added new Figure 1 and Table 1 in the GSG describing the RVfpga System
o Added a UART exercise to Lab 10.
o Fixed some typos.
RISC-V FPGA (RVfpga) is a teaching package that provides a set of instructions, tools, and labs that show how to:
– Target a commercial RISC-V system-on-chip (SoC) to an FPGA – Program the RISC-V SoC
– Add more functionality to the RISC-V SoC
– Analyze and modify the RISC-V core and memory hierarchy
The RVfpga Package provides:
– a comprehensive, freely distributed, complete RISC-V course
– a hands-on and easily accessible way to learn about RISC-V processors and the RISC-V ecosystem
– a RISC-V system targeted to low-cost FPGAs, which are readily available at many universities and companies.
After completing the RVfpga Course, users will walk away with a working RISC-V processor, SoC, and ecosystem that they understand and know how to use and modify.