module WB_RCF_ALU#(parameter NUM = 8)
(
    input wb_clk_i,
    input wb_rst_i,
    input wb_cyc_i,
    input [15:0] wb_adr_i,
    input [DATA_WIDTH-1:0] wb_dat_i,
    input [3:0] wb_sel_i,
    input wb_we_i,
    input wb_stb_i,
    output reg [DATA_WIDTH-1:0] wb_dat_o,
    output reg wb_ack_o,
    output reg wb_err_o
);

    parameter ADDR_WIDTH = 8;
    parameter DATA_WIDTH = 32;

    reg [NUM-1:0] data_in_1;
    reg [NUM-1:0] data_in_2;
    reg [NUM-1:0] data_in_3;
    reg [NUM-1:0] data_in_4;   
    wire [NUM-1:0] data_out;

    RCF_ALU #(NUM) alu (
        .clk(wb_clk_i),
        .rst(wb_rst_i),
        .data_in_1(data_in_1),
        .data_in_2(data_in_2),
        .data_in_3(data_in_3),
        .data_in_4(data_in_4),
        .data_out(data_out)
    );

    // address decode
    always @(posedge wb_clk_i or posedge wb_rst_i) begin
        if (wb_rst_i) begin
            data_in_1 <= 'd0;
            data_in_2 <= 'd0;
            data_in_3 <= 'd0;
            data_in_4 <= 'd0;
            wb_dat_o <= 'd0;
            wb_ack_o <= 0;
            wb_err_o <= 0;
        end 
        else if (wb_stb_i && wb_cyc_i) begin            
            wb_ack_o <= 1;
            if (wb_we_i) begin
                case (wb_adr_i)
                    16'h3000: begin 
                        data_in_1 <= wb_dat_i[31:24];
                        data_in_2 <= wb_dat_i[23:16];
                        data_in_3 <= wb_dat_i[15: 8];
                        data_in_4 <= wb_dat_i[ 7: 0];
                        end
                endcase
                end
            else begin
                case (wb_adr_i)
                   16'h3004:wb_dat_o <= {24'b0, data_out};
                endcase
            end 
            end 
        else begin            
            wb_ack_o <= 0;
        end
    end

endmodule