How to use the SoC alongside zynq.

Hi Rui,

Let me first say that a new version of RVfpga-SoC (1.2) was released one year ago and, in case that's not the one you are using, you should request it through the IUP website ( https://university.imgtec.com/rvfpgasoc-download-page-en/) and move to that version.

Lab 1 of RVfpga-SoC explains how to create the SoC (which is a SweRVolfX subset). For what you say, I understand that your design includes at least the same elements as the one created in that lab (specified at the end of Section 4) but please make sure that's the case:

  ● 1 SweRV Core (swerv_wrapper_verilog)
  ● 1 Interconnect Wrapper (intcon_wrapper_bd)
  ● 1 Boot-ROM (bootrom_wrapper)
  ● 1 GPIO Top Module (gpio_wrapper)
  ● 1 System Controller (syscon_wrapper)
  ● 32 Bidirec Gpio Module (bidirec)

As for programming the SoC and running programs on it, Lab 2 explains how to run programs on the SweRVolfX subset created in Lab 1. Specifically, Section 5 of Lab 2 provides details on how to run programs on the board using PlatformIO. As you can see, the process is the same as the one used in RVfpga. Maybe you can follow the same steps explained in that section and see if they work for your design.

Best regards

Dani

Thank you for your reply.

I have seen the RVfpga-SoC course, but i want to use the rvcore alongside zynq, and in the instructions i didn't see anything related to adding extra components.

I was wandering if i can use Xilinx AXI interconnect to add extra ports and connect the Zynq IP to the rest of the system. Do you have any tips related to that?

Hi Rui,

My usual suggestion is to first get what is exactly in a tutorial working.

Then make baby steps towards the destination you'd like to reach.

It can be hard to go straight towards a new design & a new board.

But it should be possible to iterate slowly towards a different system.

Once you have a simulation of a working CPU where you can see the instructions being executed.

The raw waveforms with the timestamps.

Then you can start replacing component by component.

Trying to change the interconnect, all IP blocks & connect to a new processor in one go is quite a challenge.

Thanks
Zubair

I have done the tutorial for the nexys fpga. I want to develop this in the zcu208, but i'm not being able to create the clock in the constraints, any tips on how to do it in this board?

From what i saw i allways need to include the zynq processor in these boards, is this correct?

@ruiferreira I'm afraid I don't have any direct experience with this board to be able to guide.

RVfpga itself doesn't need a zynq to be configured. But if the board requires a zynq to configure the clock module (which is a strange requirement..), I can't say

Thanks

Zubair

Posted by: @ruiferreira

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I would like to generate a block design similar to the one in the RVfpga-SoC course but in the board ZCU208 and connect the Zynq processor to the SoC design.

Any tips on how to do that? scratch geometry dash

 

Im trying to first use only the Swerv EH1 core wrapper and connect it to Xilinx IPs like the interconnect, the GPIO and the bram. This way i can connect the Zynq processor to the axi interconnect. I have successivly generated the bitstream but i'm not sure how to verify that the Swerv core is working correctly. Should I use openocd to program the core? or does that require other components that i did not include?

• Target Board Selection: Start by setting up a project in Vivado targeting the ZCU208 board.
• Swerv EH1 Core Integration: Import the Swerv EH1 core into Vivado. You may use a wrapper to interface with the core. Ensure that the core is configured correctly for your application.
• AXI Interconnect Setup: Use Xilinx AXI Interconnect IPs to connect the Swerv core to other peripherals, such as GPIO and BRAM.