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Vrvfpgasim error

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hsunyoto
(@hsunyoto)
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I've succeed in building Vrvfpgasim, but when I try to generate trace with PlatformIO from VS Code, get the same error (see below). Maybe somebody can give me a hint about what's going wrong.

 

⋊> ~/D/I/R/R/e/AL_Operations on master ⨯ pio run --verbose --target generate_trace 17:11:57
Processing rvpga (platform: chipsalliance; board: swervolf_nexys; board_build.bitstream_file: /home/harris/Downloads/Imagination_University_Programme/RVfpga_Understanding_Computer_Architecture/RVfpga/src/rvfpga.bit; board_debug.verilator.binary: /home/harris/Downloads/Imagination_University_Programme/RVfpga_Understanding_Computer_Architecture/RVfpga/verilatorSIM/Vrvfpgasim)
-----------------------------------------------------------------------------------------------------------------------
CONFIGURATION: https://docs.platformio.org/page/boards/chipsalliance/swervolf_nexys.html
PLATFORM: CHIPS Alliance (1.0.3) > RVfpga: Digilent Nexys A7
HARDWARE: 320MHz, 1.16MB RAM, 16MB Flash
DEBUG: Current (digilent-hs1) On-board (digilent-hs1, verilator, whisper) External (olimex-arm-usb-ocd, olimex-arm-usb-ocd-h, olimex-arm-usb-tiny-h, olimex-jtag-tiny)
PACKAGES:
- framework-wd-riscv-sdk 0.0.0-alpha+sha.ca4b2392d8
- tool-openocd-riscv-chipsalliance 1.1000.200713 (10.0)
- tool-verilator-swervolf 0.0.201130
- toolchain-riscv 1.80300.190927 (8.3.0)
LDF: Library Dependency Finder -> http://bit.ly/configure-pio-ldf
LDF Modes: Finder ~ chain, Compatibility ~ soft
Found 0 compatible libraries
Scanning dependencies...
No dependencies
Building in release mode
riscv64-unknown-elf-objcopy -O binary .pio/build/rvpga/firmware.elf .pio/build/rvpga/firmware.bin
riscv64-unknown-elf-objcopy: error: the input file '.pio/build/rvpga/firmware.elf' has no sections
*** [.pio/build/rvpga/firmware.bin] Error 1


   
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Valerii
(@valerii)
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Hi @hsunyoto! Could you please provide more details on how to reproduce the issue? Maybe a simple project? 


   
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hsunyoto
(@hsunyoto)
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Hi @valerii,

I've followed "Chapter 7. Simulation in Verilator" in the "RVfpga Getting Started Guide". So it is the AL_Operations project in the examples folder. I use Arch Linux.

Kind regards,

Harris


   
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Valerii
(@valerii)
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@hsunyoto Does the issue persist if you clean the project and try to generate a new trace? Please do that in verbose mode and attach the log here. Thanks!


   
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hsunyoto
(@hsunyoto)
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Hi @valerii,

Yes, I've rebuilt Vrvfpgasim several times after "make clean" with the same result. The output of "platformio run --target generate_trace --environment rvpga --verbose" is exactly like in my first post (see above).

But, I've noticed there are a lot of warnings while building Vrvfpgasim with make (see the attached output of make).

The verilator version used for building Vrvfpgasim on Arch Linux is 4.106-1.


   
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hsunyoto
(@hsunyoto)
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Posts: 11
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make.output attachment


   
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hsunyoto
(@hsunyoto)
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make_output.txt


   
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hsunyoto
(@hsunyoto)
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I cannot attach a text file on this forum. So this is the make output in PDF format.


   
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Valerii
(@valerii)
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It doesn't seem like Vrvfpgasim is the problem as the build process fails before Vrvfpgasim even starts. For some reason your ELF image is broken and that's why I asked you to clean the PlatformIO project and generate a new stream in the verbose mode so I can examine how the files are compiled and linked together.

This post was modified 2 years ago by Valerii

   
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hsunyoto
(@hsunyoto)
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This PDF file of make output is slightly easier to read than the previous one.


   
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hdzx
 hdzx
(@hdzx)
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运行“Generate Trace”时出错,出现 [generate_trace] 系统找不到指定的文件。错误的截图和输出的信息如下,已上传,谢谢。

终端输出信息如下:

> Executing task: C:\Users\XYW\.platformio\penv\Scripts\platformio.exe run --target generate_trace --environment swervolf_nexys <

Processing swervolf_nexys (platform: chipsalliance; board: swervolf_nexys; framework: wd-riscv-sdk)
--------------------------------------------------------------------------------------------------------------------------------------------

Verbose mode can be enabled via `-v, --verbose` option
CONFIGURATION: https://docs.platformio.org/page/boards/chipsalliance/swervolf_nexys.html
PLATFORM: CHIPS Alliance (1.0.3) > RVfpga: Digilent Nexys A7
HARDWARE: 320MHz, 1.16MB RAM, 16MB Flash
DEBUG: Current (digilent-hs1) On-board (digilent-hs1, verilator, whisper) External (cmsis-dap, olimex-arm-usb-ocd, olimex-arm-usb-ocd-h, olimex-arm-usb-tiny-h, olimex-jtag-tiny)
PACKAGES:
- framework-wd-riscv-sdk 0.0.0-alpha+sha.ca4b2392d8
- tool-openocd-riscv-chipsalliance 1.1000.200713 (10.0)
- tool-verilator-swervolf 0.0.201130
- toolchain-riscv 1.80300.190927 (8.3.0)
LDF: Library Dependency Finder -> http://bit.ly/configure-pio-ldf
LDF Modes: Finder ~ chain, Compatibility ~ soft
Found 0 compatible libraries
Scanning dependencies...
No dependencies
Building in release mode
Generating trace from Verilator
[generate_trace] 系统找不到指定的文件。
======================================================== [FAILED] Took 3.57 seconds ========================================================
终端进程“C:\Users\XYW\.platformio\penv\Scripts\platformio.exe 'run', '--target', 'generate_trace', '--environment', 'swervolf_nexys'”已终止,退出代码: 1。

终端将被任务重用,按任意键关闭。

Translation:

When running "Generate Trace", an error occurs and [generate_trace] system cannot find the specified file. The screenshot of the error and the output message are as follows, which has been uploaded, thank you.

The terminal output message is as follows.

> Executing task: C:\Users\XYW\.platformio\penv\Scripts\platformio.exe run --target generate_trace --environment swervolf_nexys <

Processing swervolf_nexys (platform: chipsalliance; board: swervolf_nexys; framework: wd-riscv-sdk)
---------------------------------------------------------------------------------------------------------------------------------- ----------

Verbose mode can be enabled via `-v, --verbose` option
CONFIGURATION: https://docs.platformio.org/page/boards/chipsalliance/swervolf_nexys.html
PLATFORM: CHIPS Alliance (1.0.3) > RVfpga: Digilent Nexys A7
HARDWARE: 320MHz, 1.16MB RAM, 16MB Flash
DEBUG: Current (digilent-hs1) On-board (digilent-hs1, verilator, whisper) External (cmsis-dap, olimex-arm-usb-ocd, olimex-arm-usb- ocd-h, olimex-arm-usb-tiny-h, olimex-jtag-tiny)
PACKAGES:
- framework-wd-riscv-sdk 0.0.0-alpha+sha.ca4b2392d8
- tool-openocd-riscv-chipsalliance 1.1000.200713 (10.0)
- tool-verilator-swervolf 0.0.201130
- toolchain-riscv 1.80300.190927 (8.3.0)
LDF: Library Dependency Finder -> http://bit.ly/configure-pio-ldf
LDF Modes: Finder ~ chain, Compatibility ~ soft
Found 0 compatible libraries
Scanning dependencies...
No dependencies
Building in release mode
Generating trace from Verilator
[generate_trace] The system could not find the specified file.
======================================================== [FAILED] Took 3.57 seconds ============================================== ==========
Terminal process "C:\Users\XYW\.platformio\penv\Scripts\platformio.exe 'run', '--target', 'generate_trace', '--environment', ' swervolf_nexys'" has been terminated, exit code: 1.

The terminal will be reused by the task, press any key to close it.

This post was modified 2 years ago 2 times by guanyang.he

   
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Valerii
(@valerii)
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Posts: 6
 

@hdzx Please escape the backslashes in the path to your custom Verilator. Also make sure the path is valid or better use an absolute path.


   
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Valerii
(@valerii)
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@hsunyoto For some reason your ELF image is broken and that's why I asked you to clean the PlatformIO project and generate a new stream in the verbose mode so I can examine how the files are compiled and linked together.


   
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hsunyoto
(@hsunyoto)
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Posts: 11
Topic starter  

Hi @valerii,

 

Thanks for the "hint", I've found the problem. On "Figure 81. PlatformIO initialization file: platformio.ini" ("Chapter 7. Simulation in Verilator" in the "RVfpga Getting Started Guide") the

  framework = wd-riscv-sdk

is commented out. Faithfully I also commented out this line in the "platform.ini" file which makes the build fails. I tried to build other project, and when it is successful, I compared the platform.ini files from both projects and find the culprit.

 

So, a suggestion for the author of "RVfpga Getting Started Guide" to replace the screenshot for Figure 81 with the correct one.

 

You can see in the attached file that the build is now successful, and I can generate the trace.

 


   
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guanyang.he
(@guanyang-he)
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Joined: 3 years ago
Posts: 45
 

@hsunyoto Thank you very much for pointing that out. We will update it in our next release.


   
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