RVfpga – Introduction

to RVfpgaSoC

Version 1.2

Version 1.2 (second release): 7th July 2023 

Key Changes in this version:

  • Installation Guide:
    • Pricing update of the Nexys A7. Table – 1 (Page: 03)
      • $261.75 Academic pricing (as of 7th July 2023)
      • $341 non-academic pricing (as of 7th July 2023)
    • Added: How to manually install the Chips Alliance platform in Platform IO, If it does not install automatically. (Page: 08)
    • Updated Figure 8, which now shows the execution of the multiple commands. (Page: 11)
    • Added Note: Installation of Verilator may take a long time to run.
    • Updated link to Install Verilator. (Pages: 10 & 20)
    • Specified the version of “gcc-core” and “gcc-g++” to 10.2.0 for Cygwin Installation. (Page: 18)
    • Added Note: Executing “apt upgrade” upgrades about 261+ packages which may take a while (Page: 11)
    • Added an alternate link to install/update “cmake”, if “wget” does not work for you. (Page: 12)
  • Lab 03:
    • Note: If you receive an error that the Vivado command is not found. (Page: 11)
    • Note: If “make AL_Operations.vh” fails (Page: 15)
    • Note: Save time in Labs 4 and 5 by storing export commands in a file. Simply copy the commands to a text file, save it (e.g., “my_exports.sh”), and source it in new terminal sessions or add it to your .bashrc. Streamline your workflow and effortlessly create additional terminal sessions when needed. (Page: 27)
  • Lab 05:
    • Note: If you cannot find the “example” folder (Page: 07)
Summary of package

The original release of the RVfpga SoC Design course.

This RVfpga-SoC course shows how to build a RISC-V SoC from scratch using provided building blocks and a visual block-based design approach.

The building blocks include the SweRV EH 1 CPU core, Interconnect, Boot-ROM, System controller, and GPIO controller. The SoC created by the user using the block design approach is a subset of SweRVolfX. Subsequent labs show how to run programs on the SoC, compare the block design SoC with SweRVolf made using FuseSoC, run Zephyr real-time operating system on SweRVolf, and then run a Tensorflow Lite Hello-World example on SweRVolf.

The following labs are provided:

  • Lab 1: Introduction to RVfpga-SoC
  • Lab 2: Running Software on RVfpga-SoC
  • Lab 3: Introduction to SweRVolf and FuseSoC
  • Lab 4: Running Zephyr on SweRVolf
  • Lab 5: Running Tensorflow Lite on SweRVolf

These labs show how to create an SoC from a core and other building blocks (Lab 1), how to target it to an FPGA and run programs on the newly created SoC (Labs 2), how to use a FuseSoC-based SoC (SweRVolf) for SweRV EH1 (Labs 3), how to add a real-time operating system (RTOS) to SweRVolf (Lab 4). and how to run Tensorflow Lite’s Hello World example on SweRVolf (Lab 5).