RVfpga: Understanding Computer Architecture Version 1.0 Release - 30th Nov 2020

Hi, I have joined your programme and applied for reaching your course materials. And I have a permission mail but all it can do is downloading the information sheet. When can I reach the first video? Thanks...

It's not completely clear what your issue is, so let's go through the steps:
(1) Join the IUP (you are on the Forum, so I know you've done that)
(2) Login and go to the resources page. Choose the RVfpga Teaching Materials here and follow the steps
>>>Attached is a guide to Steps 1 and 2.
 
On the Resources page, the Teaching Materials are categorised by Subject (Graphics, AI, Computer Architecture & SoC, Tools..)
Then they are sub-divided by Language. So, for example, for RVfpga, when you click on English you see Teaching Materials, Info Sheet, Links to Videos. 
More will be added to this as we build up the programme, including instructional videos.
Coming soon is our joint project with Digi-Key "Guide to RISC-V". this will be open for download soon.
Some materials you get straight away (the Info Sheet,  RISC-V Guide, link to Videos), others like the Teaching Materials take you to a request form.
- We then manually check every request, and if approved, send you a download link which is valid for 3 days.

We hope this helps you.

Dear team:

I want to use Vivado to generate .bit files based on our data pack (Workshop Materials), but I ran into some problems.

I have some confusion about the document(Workshop Materials\src\rvfpga.xdc).

I cannt find constraint pins about jtag(just like TMS/TCK/TDO/TDI) on Nexys-A7 fpga board in the rvfpga.xdc.

If there is no constraint of these pins, then how can the JTAG chip on the FPGA board be used flexibly...

Please help me about that. 

Thank you.

@sanman 

Useful information from Daniel Chaver-Martinez, RVfpga co-author & Olof Kindgren, Supporter:
- We are assuming that "data pack (Workshop Materials)" refers to the src folder that comes from the RVfpga package.

• We recommend you read carefully the post from https://github.com/chipsalliance/Cores-SweRVolf/issues/29 [github.com] and also Nexys A7 Reference Manual  https://digilent.com/reference/programmable-logic/nexys-a7/reference-manual [digilent.com], specifically Section 6. 
  - The main parts of the post that may answer your question are the following:
  • The bscan_tap module in SweRVolf is a wrapper over Xilinx BSCANE2 primitives, provided only as black-box IP blocks by Xilinx. BSCANE2 allows to connect the user's custom design to the JTAG TAP of the FPGA component. It works this way: If the JTAG debugger writes one of the special "user instructions" to the FPGA's JTAG instruction register, the following JTAG data scans will go directly to the user design through the BSCANE2 instances. In SweRVolf, this mechanism is utilized to expose SweRV's JTAG registers of SweRV in the JTAG TAP of the FPGA.
  • I guess the other half of the answer is why we do it like this. On the Nexys A7 board, the dedicated FPGA JTAG pins are connected to an FTDI chip together with the UART channel. This way we only need to connect a single USB cable to the board for power, UART and JTAG instead of requiring a separate JTAG adapter. In extension, by exposing the debug interface from the CPU instead of the JTAG pins, this allows us to tunnel the debug interface over basically any connection. Not all FPGA boards have JTAG-to-USB or even convenient user-accessible I/O pins. We could e.g. do debug over ethernet or debug over UART or debug over pciE if those are more convenient ways to access the SoC on other board.