Notifications
Clear all

[Sticky] RVfpga v2.0 released today!

 

Jingyang Liu
(@jingyang-liu)
Member Admin
Joined: 5 months ago
Posts: 16
Topic starter  

We’ve just released RVfpga 2.0!

This version extends the existing materials (the Getting Started Guide and Labs 0-10) by adding Labs 11-20, creating enough materials to support two semesters of teaching.

 Labs 11-20 focus on microarchitecture and memory hierarchy., and they explore the SweRV EH1 RISC-V pipeline and use or add features to the RISC-V core, including:

*Using and adding performance counters

*Analysing basic instructions (arithmetic-logic, memory, branch) and adding new ones

*Analysing how structural, data and control hazards are handled

*Using the branch predictors

*Enabling the scratchpad memories (DCCM and ICCM)

*Using testbenches to measure performance, and exploring various memory features.

 

We would also like to highlight that the complementary RVfpga-SoC course, released in June 2021, is now available in 5 languages.

 

This topic was modified 6 months ago by

   
RCWO reacted
Quote
alanmaxwell
(@alanmaxwell)
New Member
Joined: 1 year ago
Posts: 1
 

where can I get the download link?


   
dileep reacted
ReplyQuote
dchaver
(@dchaver)
Member Moderator
Joined: 2 years ago
Posts: 48
 

Hi @alanmaxwell 

In the following link you can find all the information for download: https://university.imgtec.com/rvfpga/

Best regards


   
ReplyQuote
Richard-Alexander-5
(@richard-alexander-5)
New Member
Joined: 1 year ago
Posts: 3
 

Good night dear experts.

I have a question about RVfpga_Lab20. There are some parameters like: Coremark size, total ticks, total time (secs), iterations/sec, iterations and others. Where can I find what all these parameters mean. The second question is something that I have read in the same lab. In figure 8, the parameter total time is 2099 secs. Why that parameter is so high? When I execute the benchmark, it just takes a few seconds.


   
ReplyQuote
dchaver
(@dchaver)
Member Moderator
Joined: 2 years ago
Posts: 48
 

Dear Richard Alexander,

There are several webpages where you can find interesting descriptions about the CoreMark benchmark, such as https://www.eembc.org/coremark/ or https://github.com/GaloisInc/BESSPIN-coremark . Besides, in folder RVfpga/Labs/Lab20/RealBenchmarks/CoreMark_HwCounters/src you can find file cmark.c which contains the benchmark source and from where you can see how these parameters are used and infer their meanings. Anyway, let me describe next the meaning of the main parameters:
   - Size: This is the buffer size used by the program, defined through parameter TOTAL_DATA_SIZE and measured in bytes.
   - Total Ticks: Number of cycles required to execute the benchmark. Note that function get_time is used for this purpose (total_time=get_time();), which is implemented in the cmark.c file.
   - Iterations: It controls how many times the CoreMark kernel is executed.

The time in seconds shown in Figure 8 is wrong. You are right. The problem is that we didn't update the default parameter #define EE_TICKS_PER_SEC 1000 according to our system. We will correct this issue in our next release. Thanks a lot for your observation.

Best regards

Dani


   
ReplyQuote
sanman
(@sanman)
New Member
Joined: 1 year ago
Posts: 2
 

Dear Team:

We're using SweRV EH1. I'm not familiar with this CPU, and I don't see an easy-to-understand description on its website.

Can I port Linux on this core? Is it possible to run the OS on SweRV EH1 based on the Nexys A7 FPGA Board?

Please help me solve this puzzle.

thank you


   
ReplyQuote
RCWO
 RCWO
(@rcwo)
Member Admin Registered
Joined: 3 years ago
Posts: 53
 

Dear @Sanman

The EH1 is intended as an embedded control CPU - more MCU than MPU - so it does not include an MMU (Memory Management Unit). Therefore it cannot run an OS like Linux.
Our RVfpga Introduction to SoC course shows you how to put the Zephyr RTOS on to the EH1.

Our RVfpga: Understanding Computer Architecture course goes in-depth to many aspects of the EH1.
You can also find lots of additional info from Western Digital, one of our key partners, here:
- https://www.westerndigital.com/en-gb/solutions/risc-v

There's also a very interesting and extensive video describing, among other things, the SweRV microarchitecture:
https://www.youtube.com/watch?v=ODU1b9amCG8 [youtube.com]

AND, another important reference is the Chips Alliance Github, which includes a complete repository for each core, including documentation:
- https://github.com/chipsalliance/Cores-SweRV [github.com]
- https://github.com/chipsalliance/Cores-SweRV-EH2 [github.com]
- https://github.com/chipsalliance/Cores-SweRV-EL2 [github.com]

Of course, the most detailed documentation for EH1 is provided in RVfpga!

Hope this helps you.

Best Wishes, Robert Owen

This post was modified 7 months ago by RCWO

   
ReplyQuote
Jingyang Liu
(@jingyang-liu)
Member Admin
Joined: 5 months ago
Posts: 16
Topic starter  

这个版本扩展了现有的材料(入门指南和实验室0-10),增加了实验室11-20,创造了足够的材料来支持两个学期的教学。

实验室11-20侧重于微架构和内存层次,它们探索了SweRV EH1 RISC-V流水线,并使用或增加了RISC-V内核的功能,包括: *使用和增加性能计数器。
*使用和增加性能计数器
*分析基本指令(算术-逻辑、内存、分支)并添加新指令
*分析如何处理结构、数据和控制的危险性
*使用分支预测器
*启用刮板存储器(DCCM和ICCM)。
*使用测试平台来测量性能,并探索各种存储功能。


   
ReplyQuote