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Cannot generated trace.vcd using the PlatformIO  

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wenyeliu
(@wenyeliu)
Active Member
Joined: 6 months ago
Posts: 8
06/05/2022 11:33 am  

Hi,

 

I follow the RVfpga_GettingStartedGuide v2.1 to setup all the tools and drivers.

The whole process is smooth except in the Section 7 Simulation in Verilator.

I am runing this package in Win10, the Vrvfpgasim.exe has been compiled and setted as board_debug.verilator.binary in the platformio.ini file.

By clicking the Generate Trace button, the terminal outputs a log with "Generating trace from Verilator" and a success. However, there is no trace.vcd file generated inside [RVfpgaPath]/RVfpga/examples/AL_Operations/.pio/build/swervolf_nexys. I also try to run command in the PlatformIO terminal, still no trace.vcd file generated.

On the other hand, runing the Vrvfpgasim.exe directly in the cygwin terminal by inlucding the +ram_init_file and +vcd=1 can generated the vcd file.

I want to ask if I miss any setting in the PlatformIO to generate the waveform file?

 

Best regards,

Wenye


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dchaver
(@dchaver)
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Joined: 2 years ago
Posts: 41
08/05/2022 2:32 pm  

Hi @wenyeliu 

The process that you are describing looks good.

Anyway, I've tested Section 7 of the GSG in my Windows 10 VM and everything works fine. I've made a video so that you can compare the process I've followed with yours. Let me know if you're still having problems.

https://drive.google.com/file/d/11CIeyWx2wgc-TCi3I7bGOT_87RxbxcGK/view?usp=sharing

Best regards

Daniel

This post was modified 3 months ago by dchaver

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dchaver
(@dchaver)
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Posts: 41
08/05/2022 3:34 pm  

Hi,

Please find the video attached.

Best regards

Daniel


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wenyeliu
(@wenyeliu)
Active Member
Joined: 6 months ago
Posts: 8
09/05/2022 9:19 am  

Hi Daniel,

Thanks for your video. I compare the versions and steps. They are the same (PlatformIO 5.2.5, CHIPS Alliance 1.1.0). Even the terminal output looks the same where the firmware.bin and firmware.vh can be generated. The only difference is just missing the trace.vcd waveform file. I tried both v4.106 and v4.222 of Verilator.

Anyway, I still can use the verilator in the command mode to dump the waveform. So I can continue on the RVfpga course.

Best regards,

Wenye


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dchaver
(@dchaver)
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Joined: 2 years ago
Posts: 41
09/05/2022 10:38 am  

Hi Wenye,

Do you want to test the executable that we are using, to see if that is the problem? I'm attaching it as a zip file.

Best regards,

Dani


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wenyeliu
(@wenyeliu)
Active Member
Joined: 6 months ago
Posts: 8
11/05/2022 10:17 am  

Hi Daniel,

Your executable works!!!! I can generate the trace.vcd in the PlatformIO by pointing the verilator binary to your provided file. I compare the size of your executable (8,163,865 bytes) and mine (6,385,276 bytes), they are different. 

I am facing anohter issue on Lab6 which I need to do the simulation on verilator. The o_gpio signals just not change by following the change of the i_gpio signals. I doubt it is also related to the issue of the verilator. Any suggestion that I can compile the verilator executable as yours? The log of my compilation is attached.

 

Best regards,

Wenye

 


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dchaver
(@dchaver)
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Joined: 2 years ago
Posts: 41
12/05/2022 4:34 am  

Hi @wenyeliu,

I cannot see any attachment in your post. I don't know if you forgot to include it or if there is any problem with the web. It would be very useful to be able to see it. If you forgot to include it, please do it; meanwhile, I'll ask to Imagination in case there is any problem in the webpage.

Did you follow the exact same steps that are described in Section 7 - "GENERATE THE SIMULATION BINARY, Vrvfpgasim" and in Appendix C for installing Cygwin? Also, take into account the information published in the following post: https://university.imgtec.com/forums/rvfpga/package-versions-that-work-with-rvfpga-v-2-1-on-windows-10-compile-verilator/

Best regards

Dani


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wenyeliu
(@wenyeliu)
Active Member
Joined: 6 months ago
Posts: 8
12/05/2022 8:10 am  

Hi Dani,

I try to attach the log again. Actually I do encounter some web error warning last time when I click the reply button.

For the Vrvfpgasim generation, I use the following the steps, "make clean" and "make -j 6".

Best regards,

Wenye


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wenyeliu
(@wenyeliu)
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Joined: 6 months ago
Posts: 8
12/05/2022 8:11 am  

Seems the attachment is still cannot be uploded......


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wenyeliu
(@wenyeliu)
Active Member
Joined: 6 months ago
Posts: 8
12/05/2022 8:15 am  

Please find the output log through this link https://www.dropbox.com/s/54biafbz0nshobl/output_verilator.log?dl=0

Best regards,

Wenye


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dchaver
(@dchaver)
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Joined: 2 years ago
Posts: 41
12/05/2022 2:29 pm  

Hi Wenye,

I'm attaching the output that I obtain when I compile Verilator in my Windows 10 VM. You'll see that it's different than yours (I've not analysed it in detail). Can you please try to download the RVfpga package again and test the compilation again? Note that, if you do that, you'll be downloading v2.2, which includes a slightly different organization of the directories and some new files (mainly related with WS materials), but which changes nothing related with verilator or the SoC sources.

Best regards

Dani


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dchaver
(@dchaver)
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wenyeliu
(@wenyeliu)
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Joined: 6 months ago
Posts: 8
13/05/2022 1:56 am  

@dchaver Thanks Daniel.

I have submitted the download request. Will try on the v2.2. 


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dchaver
(@dchaver)
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Posts: 41
13/05/2022 5:16 am  

Great Wenye. Let me know once you've tested. I'm attaching the verilator output.

Best regards


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wenyeliu
(@wenyeliu)
Active Member
Joined: 6 months ago
Posts: 8
13/05/2022 1:36 pm  

@dchaver Hi Daniel,

Finally, the compiled executable works. I confirm that using the same version of the packages listed in the post:  https://university.imgtec.com/forums/rvfpga/package-versions-that-work-with-rvfpga-v-2-1-on-windows-10-compile-verilator/ is necessary to generate a working executable of verilator. Previously, I am using newer versions of the gcc-core and gcc-g++ which might be the cause for such abnormal behaviour.

Thank you for your patience and help!

Best regards,

Wenye


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