Errors occur when I try to generate Vrvfpgasim.(GSG,chapter 7)
From the information that you've shared, it looks to me as if you were using a mixture of two RVfpga versions. In November we released v1.0 and in June we released v1.1. In the new version we included, among other things, an upgrade of the Verilator version as well as some reorganization of the RVfpga/src directory.
- What RVfpga version are you using? Have you used both of them?
- What Verilator version are you using?
- File /RVfpga/verilatorSIM/swervolf_0.7.vc defines the paths to the different files that make up the SoC, and it has some differences between the two RVfpga versions. Can you check if your /RVfpga/verilatorSIM/swervolf_0.7.vc file is coherent with the organization of your RVfpga/src directory?
Maybe the easiest solution is to completely remove the RVfpga directory and download v1.1 again.
Let me know if you can solve the problem with these instructions; otherwise, please provide some more information about the steps that you are following.
-I used the Chinese version 1.0 only which named RVfpga_Simplified_Chinese_v1.0.
-File /RVfpga/verilatorSIM/swervolf_0.7.vc is obviously incoherent to RVfpga/src directory as I show in the PNG.(Where, 1.PNG show .../src directory, 2.PNG show .../src/SweRVolfSoc directory, and 3.PNG show a part of file swervolf_0.7.vc.
I will re-download the English version (v1.1) and try again later. And if it works, I will let you know.
Hi again @theyuexia,
I think we've detected the problem. It looks like the Chinese packages have some files missing in the SoC sources (RVfpga/src). We'll correct the packages as soon as possible. Meanwhile, you can request and use the English package (either v1.0 or v1.1).
Sorry for the inconvenience.