Help with adding a new IP to the peripherals
I want to add a basic matrix multiplication IP to the SoC, however I could not find any resources for that integration.
The Labs 06-10 show how to add extra peripherals to the system, but i did not understand how to translate that to a custom IP.
Can you give us more details about the specific IP that you intend to use and what you have tried so far? Are you using Vivado’s Block Design feature? In RVfpga, Labs 6-10, we only explain how to add new Wishbone open-source periperals to the RVfpga-SoC directly in Verilog. I'm not sure if this approach will be valid in your case. You may find more useful RVfpga-SoC, a different teaching package that you can find at: "https://university.imgtec.com/rvfpgasoc-download-page-en/". In this course, labs 1 and 2 show how to create a reduced RVfpga-SoC using Vivado’s Block Design.
Let us know if this helps and if you have more questions.
@dchaver my goal is to add a simple matrix multiplication IP to the SoC. I went through the first 3 labs of the RVfpga-SoC course already, however the IP that i have uses AXI interface. Because of this i thought I would need to develop a new IP that uses wishbone instead, similar to the peripherals described in the Labs 06-10.
I have am trying to create a new peripheral similar to the counter (since it's the only one that does not use any physical pins) but i don't really know what I'm doing.
I am not trying to use vivado's block design feature since my IP is not made to work with wishbone and I don't know how to create an IP that uses wishbone.
I also don't know what the best approach to my problem is since i am still learning, but the approach described in the RVfpga course seemed best, since i can learn from the examples.
Any guidance you can give me for my problem?
Thank you for all the help you have given me already.
Developing a Wishbone peripheral would allow you to use exactly the same procedure explained in Labs 6 and 8 for the Wishbone new peripherals, however it can be a bit difficult. Unfortunately, as you've seen, we explain how to integrate open-source peripherals, but not how to build them, and they are quite complex. Do you think you'll be able to do it? Do you want to keep trying this? Maybe you can try to find an open-source Wishbone peripheral that meets your requirements.
Another option would be to directly connect the AXI peripheral to the SoC, however, we do not explain this process in RVfpga v2.2 nor have ever tried it. Would you prefer this second way?
@dchaver I will try to find an open-source peripheral that meets my requirements and use the methods shown in RVfpga v2.2 as you suggested.
If I am not unable to find the peripheral I am looking for I will try to build my own. Do you have any resources that you could give me to guide me in the development of the peripheral?
Once again, thank you for all your help.
I've never done that, but I'd not start from one like the ones we're using from Open Cores, as those include many functionalities (such as interrupt support) and thus are quite complex. I'd try to start instead from a simple one. Please first look for an open-source peripheral that meets your requirements and if you don't find it, ask us again.
Let us know about your progresses
BTW, let me add some useful information which is not included in RVfpga v2.2 and that can be useful to generate the extended multiplexer.
You can also automate the process of extending the multiplexer with the help of a script instead of doing it by hand. For that purpose, follow the next steps:
python3 wb_intercon_gen2.py config.yml
For example, a config.yml file that creates a multiplexer for the default peripherals plus the pushbuttons would look like this:
files_root: . vlnv: ::wb_intercon:0 parameters: masters: io: slaves : [rom, sys, spi_flash, spi_accel, ptc, gpio, gpio2, uart] slaves: rom: offset : 0x00000000 size : 0x00001000 sys: offset : 0x00001000 size : 0x00000040 spi_flash: offset : 0x00001040 size : 0x00000040 spi_accel: offset : 0x00001100 size : 0x00000040 ptc: offset : 0x00001200 size : 0x00000040 gpio: offset : 0x00001400 size : 0x00000040 gpio2: offset : 0x00001800 size : 0x00000040 uart: offset : 0x00002000 size : 0x00001000
You will obtain the two files that implement the multiplexer, wb_intercon.v and wb_intercon.vh, which you can then use in your extended SoC.
I think that for my project it's better to add the peripheral directly to the AXI bus. Is it possible to add a third slave to the bus, next to the RAM and the bridge to the wishbone bus?
I found a generic AXI interconnect fabric on OpenCore (link now broken) but i am not able to download the RobustVerilog parser provided.