Hello every one,
I am interested in porting RVfpga to Nexys Video board. Compare to Nexyx A7, it has DDR3 instead of DDR2. So I should change the files in the LiteDRAM folder.
- What is the procedure to migrate from DDR2 to DDR3?
- Can I generate new files with Xilinx MIG IPcore and replace these files?
Best,
Amir
- Did you use litedram (A small footprint and configurable DRAM core powered by Migen & LiteX) from https://github.com/enjoy-digital/litedram to generate sources in LiteDRAM folder ?
- Can I follow the same procedure to generate DDR3 interface?
@amir
The delay in answering is because of a debate about priorities. We are a small team (3 people) and we focus on one major project at a time. Right now, we have just completed the RVfpga EdX course and we are now working to complete the port to the smaller EL2 core and the Basys3 and Boolean Board platforms.
To answer your request would require stopping this and moving to a different board. After careful consideration, we cannot do this. Your board is not a priority.
Our apologies - you will need to find other sources of help if you wish to do this.
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