[Solved] Vivado 2019.2 installer can´t connect to internet

Hi Rui,

It's the first time I hear about this problem and it's not easy to replicate it to be able to investigate it, so I don't really have a specific answer for your question. Let me give you some ideas and let's see if you can resolve it. Otherwise, I can try to look at the issue in more detail, in which case I'd need to know more information such as the OS you are using, the steps that you could complete and those that you couldn't, etc. These are my ideas:

1. Try to completely uninstall Vivado and then reinstall it from scratch. Note that for uninstalling it completely you may need to delete some files by hand.
2. Use a more modern version of Vivado in which RVfpga should also work. For example I've recently been using Vivado 2022.2. Minor changes in the project configuration are required (if you want to try this option, I can share more information with you).
3. I've found several posts in the Internet talking about similar problems to yours. I've looked in Google for something like "vivado the installer could not connect to the Internet". You can try the solutions proposed there. 
4. You can try to post your question in the Xilinx forum, where there will for sure be people more experienced in Vivado.

Let us know your progress and if you need more help.
Best regards
Dani

中文翻译：

1. 尝试完全卸载 Vivado，然后从头开始重新安装。 请注意，要完全卸载它，您可能需要手动删除一些文件。
2. 使用更现代的 Vivado 版本，其中 RVfpga 也应该可以工作。 例如，我最近一直在使用 Vivado 2022.2。 需要对项目配置进行少量更改（如果您想尝试此选项，我可以与您分享更多信息）。
3. 我在互联网上发现了几篇帖子，讨论与您类似的问题。 我在 Google 中查找过类似“vivado 安装程序无法连接到互联网”的内容。 您可以尝试那里提出的解决方案。
4. 您可以尝试在 Xilinx 论坛中发布您的问题，那里肯定会有更有 Vivado 经验的人。

@dchaver thank you for your reply. I am trying to synthesize the design in version 2022.2 and correct the errors as they come. However a new error appeared that i am not able to fix and could not find any fix on google.

The error message is: [Synth 8-10976] multiple packed dimensions are not allowed in this mode of Verilog

The line that the error is pointing has: wire [ 7:0] [ 7:0] enable

中文翻译：

Hi @ruiferreira,

I think that problem should get resolved if you change the type of file "RVfpga/src/SweRVolfSoC/Peripherals/SystemController/swervolf_syscon.v" to System Verilog. You can do that by either renaming the file to swervolf_syscon.sv (make sure that the changes apply to your Vivado project) or by right-clicking on the file in Vivado and setting it manually to System Verilog.

中文翻译：

我认为如果将文件“RVfpga/src/SweRVolfSoC/Peripherals/SystemController/swervolf_syscon.v”的类型更改为系统 Verilog，这个问题应该得到解决。 您可以通过将文件重命名为 swervolf_syscon.sv（确保更改适用于您的 Vivado 项目）或右键单击 Vivado 中的文件并将其手动设置为 System Verilog 来实现此目的。

Please let us know if the problem gets resolved.

Best regards

Dani

Yes it fixed the problem.

Thank you for all your help.