How to simulate SweRV core in vivado
Question credits to Prof. Libo Chang
We want to add the acceleration unit containing the IP core provided by Xilinx to the SoC system based on the SweRV core. Hence, we hope that it can be simulated on the vivado software platform of xilinx. But I don't know how to load the instructions generated by the compiler into the simulation platform. Could you please give some advice?
Hi Prof. Chang 常教授您好
As you might know, RVfpga and RVfpga-SoC do not include support for Vivado XSIM simulator. They are based on SweRVolf v0.7.3, which does neither support this simulator, and we discarded XSIM for RVfpga after several unsuccessful attempts. However, I've just seen that SweRVolf v0.7.4, the latest SweRVolf release, does include support for Xilinx's simulator (see the notes provided at https://github.com/chipsalliance/Cores-SweRVolf/releases [github.com]: "Xilinx XSim support: In addition to official support for ModelSim/QuestaSim and Verilator, SweRVolf can now also be simulated with Vivado XSim (versions 2020.1 and later)"). (Need to be confirmed)
So, I'd ask you to clarify exactly what they have been using so far (SweRV, SweRVolf, RVfpga?) and which specific versions, and also to suggest you to try, if they haven't yet, the Vivado simulation with SweRVolf v0.7.4 ( https://github.com/chipsalliance/Cores-SweRVolf/tree/v0.7.4 [github.com]).
As for the program to simulate, it is usually included as a simulation source in the Vivado project.
You can see the detailed instructions of the RVfpga simulation in Section 7 and Appendix A of the RVfpga GSG (although these instructions are for Verilator, they can help them for the XSIM simulation). MIPSfpga included support for XSIM and detailed instructions about how to use it, so it could also be useful for them to look at the MIPSfpga GSG.
@jingyang-liu Is there any update to get RVfpga to use SweRVolf v0.7.4? Being able to support Vivado simulations and possibly others like ModelSim would be nice. I also had students try to synthesize RVfpga to a standard cell design and ran into many problems; I wonder if SweRVolf v0.7.4 would be better for ASIC synthesis too.
This stimulated some discussions. Here's the consensus from our Authors:
"Changing RVfpga to the newest SweRVolf version would take several weeks of work. Being able to use XSim would be nice, but I don't think that it is so important. Besides, the current version has been tested by many persons for more than one year and is quite robust. So we do not plan to update now. We have some higher priorities: completing the EdX board (with ViDBo Virtual Dev Board), and perfecting the lower-cost course using the EL2 core and Basys3 FPGA board."
Olof Kindgren may have some comments about the lower level details of the differences between v0.7.3 and v0.7.4.
He may also have a useful input on the ASIC question.