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How to simulate SweRV core in vivado

 

Jingyang Liu
(@jingyang-liu)
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Question credits to Prof. Libo Chang

 

由于我们想将包含xilinx提供IP核的加速单元,加入到基于SweRV核的SoC系统中,因此希望可以在xilinx的vivado软件平台上仿真。但是日前不知道怎么将编译器生成的指令加载到仿真平台中。

 

We want to add the acceleration unit containing the IP core provided by Xilinx to the SoC system based on the SweRV core. Hence, we hope that it can be simulated on the vivado software platform of xilinx. But I don't know how to load the instructions generated by the compiler into the simulation platform. Could you please give some advice?

Many thanks


   
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Jingyang Liu
(@jingyang-liu)
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Hi Prof. Chang 常教授您好

 

As you might know, RVfpga and RVfpga-SoC do not include support for Vivado XSIM simulator. They are based on SweRVolf v0.7.3, which does neither support this simulator, and we discarded XSIM for RVfpga after several unsuccessful attempts. However, I've just seen that SweRVolf v0.7.4, the latest SweRVolf release, does include support for Xilinx's simulator (see the notes provided at https://github.com/chipsalliance/Cores-SweRVolf/releases [github.com]: "Xilinx XSim support: In addition to official support for ModelSim/QuestaSim and Verilator, SweRVolf can now also be simulated with Vivado XSim (versions 2020.1 and later)"). (Need to be confirmed)

So, I'd ask you to clarify exactly what they have been using so far (SweRV, SweRVolf, RVfpga?) and which specific versions, and also to suggest you to try, if they haven't yet, the Vivado simulation with SweRVolf v0.7.4 ( https://github.com/chipsalliance/Cores-SweRVolf/tree/v0.7.4 [github.com]).

As for the program to simulate, it is usually included as a simulation source in the Vivado project.

You can see the detailed instructions of the RVfpga simulation in Section 7 and Appendix A of the RVfpga GSG (although these instructions are for Verilator, they can help them for the XSIM simulation). MIPSfpga included support for XSIM and detailed instructions about how to use it, so it could also be useful for them to look at the MIPSfpga GSG.

 

您可能知道,RVfpga 和 RVfpga-SoC 不支持 Vivado XSIM 模拟器。它们基于 SweRVolf v0.7.3,它不支持此模拟器,在几次尝试不成功后,我们放弃了在RVfpga上使用 XSIM。但是,我刚刚看到最新的 SweRVolf 版本 SweRVolf v0.7.4 确实支持 Xilinx 模拟器(请参阅 https://github.com/chipsalliance/Cores-SweRVolf/releases [github.com] 上提供的说明:“Xilinx XSim 支持:除了对 ModelSim/QuestaSim 和 Verilator 的官方支持,现在还可以使用 Vivado XSim(2020.1 及更高版本)模拟 SweRVolf”。(需要确认)
 
所以,我想请您说明一下他们到目前为止一直在使用什么(SweRV、SweRVolf、RVfpga?)以及哪些具体版本?您还可以尝试使用 SweRVolf 进行 Vivado 模拟v0.7.4 ( https://github.com/chipsalliance/Cores-SweRVolf/tree/v0.7.4 [github.com])。
 
至于要仿真的程序,通常作为仿真源包含在 Vivado 工程中。
 
您可以在 RVfpga GSG 的第 7 节和附录 A 中查看 RVfpga 模拟的详细说明(虽然这些说明是针对 Verilator 的,但它们可以帮助他们进行 XSIM 模拟)。 MIPSfpga 包括对 XSIM 的支持以及有关如何使用它的详细说明,因此查看 MIPSfpga GSG 也可能对他们有用。
 
Best wishes
IUP Team

   
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bcruiksh
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@jingyang-liu Is there any update to get RVfpga to use SweRVolf v0.7.4?  Being able to support Vivado simulations and possibly others like ModelSim would be nice.  I also had students try to synthesize RVfpga to a standard cell design and ran into many problems; I wonder if SweRVolf v0.7.4 would be better for ASIC synthesis too.

 

Thanks,

Brian


   
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RCWO
 RCWO
(@rcwo)
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Dear Brian,
This stimulated some discussions. Here's the consensus from our Authors:

"Changing RVfpga to the newest SweRVolf version would take several weeks of work. Being able to use XSim would be nice, but I don't think that it is so important. Besides, the current version has been tested by many persons for more than one year and is quite robust. So we do not plan to update now. We have some higher priorities: completing the EdX board (with ViDBo Virtual Dev Board), and perfecting the lower-cost course using the EL2 core and Basys3 FPGA board."

Olof Kindgren may have some comments about the lower level details of the differences between v0.7.3 and v0.7.4.
He may also have a useful input on the ASIC question.

Best Regards,

Robert Owen


   
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