Use Vivado to simulate the Swervolf core  


Libo Chang
New Member
Joined: 10 months ago
Posts: 1
11/08/2022 12:01 am  


Since we need to increase the IP provided by Xilinx to  SoC based on the RISC-V , we need to simulate under Vivado. But we don't know how to store the instructions produced by the compiler.