Lab 1 error with Vivado 2021.1 on Manjaro

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JiaChen

(@jiachen)

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Joined: 3 years ago

Posts: 2

Topic starter 27/08/2021 3:27 pm

Hi, I followed all the lab instruction steps in lab 1 but failed to generate a bitstream.

3 errors existed.

[HDL 9-3952] use of undefined macro 'AXI_TYPEDEF_AW_CHAN_T' ["/home/kaminari/RVFPGA/RVfpga/src/SweRVolfSoC/Interconnect/AxiInterconnect/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv":402]

[Synth 8-1717] cannot access memory enable directly ["/home/kaminari/RVFPGA/RVfpga/src/SweRVolfSoC/Peripherals/SystemController/swervolf_syscon.v":337]

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JiaChen

(@jiachen)

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Joined: 3 years ago

Posts: 2

Topic starter 27/08/2021 4:26 pm

Problem solved. Set swervolf_syscon.v to be sv file tyoe

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