I am trying to generate the bitstream in Vivado in order to add Floating Point operations support, but when I try to do so, I get an error indicating "module 'adder' not found", where adder is the fpu unit that performs the floating point addition. I have checked the files inside the "RVfpga/src" folder and compared them with the ones provided by the solution, and as far as i have been able to see, they are all the same. The only difference is that I have also enabled support for min/minu/max/maxu instructions. The Vivado project is configured as explained in lab 5.
It is also worth mentioning that I got a similar error when generating the Vrvfpgasim file, and I fixed it by copying the adder.v and similar files to "/RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/include"
I am using Vivado 2019.2 and Ubuntu 22.04.3 LTS, and i was able to generate the bitstream for just the min/minu/max/maxu instructions, and for the solutions files provided, but I want to generaste a bitstream that supports both features.
Hello Alfonso,
First of all, let me ask you some things:
- Are you using RVfpga v3.0 or v2.2? I'd recommend you to request v3.0 ( https://university.imgtec.com/rvfpga-el2-v3-0-english-downloads-page/) and start using it, if you're not doing it yet.
- Are you using EH1 with Nexys A7, or EL2 with one of the new boards? From your screenshot I understand you use EH1, but please confirm that.
- Which OS are you using? Are you using the Virtual Machine provided in v3.0?
Assuming you are using EH1, in the solutions folder you should find the adder module (as well as the multiplier and divider modules). This is the path in my computer (look also at the attached screenshot):
~/RVfpga/RVfpgaEH1/RVfpga/Labs/RVfpgaLabsSolutions/Modified_RVfpgaSystem/RVfpgaSystem_Lab18/FloatingPoint/src/SweRVolfSoC/SweRVEh1CoreComplex/exu
Can you find it?
Note also that, when you create the new Vivado project, you need to specify the src directory that includes the adder module. In that case, you should not have errors when generating the bitstream.
Please let us know your progress and if you need more help.
Best regards
Dani
Hello,
I have managed to fix the probem by creating a brand new Vivado project. I don't know if the problem was caused because of using the same project I created for the Min/minu/max/maxu instructions, or if I had something else that was not properly configured, but now it works fine.
I am using RVfpga 2.2, EH1 with Nexys A7, and my own Linux distribution, Ubuntu 22.03 LTS
Sorry for the inconvenience caused and thank you for your help.
Regards,
Alfonso
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