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rvfpga Synthesis Error in Vivado

 

(@atsheikh)
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Joined: 3 years ago
Posts: 2
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Please see the attached figure that describes the synthesis error that I am facing while doing lab 1.


   
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dchaver
(@dchaver)
Member Admin
Joined: 3 years ago
Posts: 70
 

Hi @atsheikh,

It's strange that you obtain this error, as Lab 1 has been tested several times by different people. Are you using Vivado 2019.2? Are you sure that you are following exactly the same steps described in that lab for synthesizing?

Anyway, I think that you should be able to resolve the problem by redefining that file as System Verilog, which does support multiple packed dimensions. You can do that in different ways: one is to modify the file type to System Verilog in the Source File Properties window (see attached screenshot). 

Let us know if you can resolve your problem or you need more help.

Best regards


   
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(@atsheikh)
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Joined: 3 years ago
Posts: 2
Topic starter  

@dchaver It worked. Many Thanks.


   
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(@matthewlai)
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Joined: 2 years ago
Posts: 3
 

I ran into the same problem with Vivado 2020.1 in Windows. Changing the file type to SystemVerilog resolves the issue 😀


   
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