rvfpga Synthesis Error in Vivado
Please see the attached figure that describes the synthesis error that I am facing while doing lab 1.
It's strange that you obtain this error, as Lab 1 has been tested several times by different people. Are you using Vivado 2019.2? Are you sure that you are following exactly the same steps described in that lab for synthesizing?
Anyway, I think that you should be able to resolve the problem by redefining that file as System Verilog, which does support multiple packed dimensions. You can do that in different ways: one is to modify the file type to System Verilog in the Source File Properties window (see attached screenshot).
Let us know if you can resolve your problem or you need more help.