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[Solved] Numerous errors and warnings at compile time of Vrvfpgasim

 

(@sosta)
New Member
Joined: 12 months ago
Posts: 1
Topic starter  

Hi there,

 

I ran into many warnings and errors when compiling the Vrvfpgasim with Verilator which was eventually causing the compilation to fail (> 50 errors).

 

The majority of the warnings were related to `PINMISSING`, `WIDTHTRUNC`, `UNOPTFLAT`, and `WIDTHEXPAND` but more importantly, the errors were all related to a missing timing flag in the provided Makefile:

%Error-NEEDTIMINGOPT: ../src/SweRVolfSoC/Peripherals/ptc/ptc_top.v:255:19: Use --timing or --no-timing to specify how timing controls should be handled
                                                                         : ... In instance rvfpgasim.swervolf.timer_ptc

After some digging around in the Verilator Github Issues, I found that, since Verilator 5.002 2022-10-29, either --timing or --no-timing compiler flags need to be provided.

 

I was able to successfully compile the Vrvfpgasim binary by adding either one of those flags to the Verilator options in the Makefile but I am left with a few questions:

  1. Will I run into other eventual issues given the warnings mentioned above? (I can provide the full g++ output if more info is required there)
  2. I assumed that using the `--timing` flag was a better option than `--no-timing` but would like to know if that was the correct assumption or not?

 

System & software info of my set-up:

  • OS: Arch Linux x86_64 v2023.03.01
  • Kernel: 6.2.6-arch1-1
  • Verilator: v5.008 2023-03-04
  • GCC version: 12.2.1 20230201
  • GNU Make: v4.4.1

Thank you in advance for the help!

This topic was modified 12 months ago by sosta

   
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(@danichaver)
New Member
Joined: 2 years ago
Posts: 2
 

Hello Sosta,

I'm a Ubuntu user. Currently I'm using Ubuntu 22.04, which installs v4.038 of Verilator by default. In this version the flags timing/no-timing are not necessary. This is the Verilator version that we've been using for several months, and in which all our Verilator-based simulators (both the one generating the vcd trace, that the RVfpga package provides, and the ones using ViDBo and the Pipeline Simulator) have worked correctly. Thus, this is the version that we recommend to use as it's been highly verified by many people.

For being able to make tests with Verilator v5, I've just manually installed v5.009 in my system and, as you say, using --timing and --no-timing flags compiles the Verilator-based simulators correctly (not using these flags gives the errors that you mention). However, I've not been able to make any other tests yet.

So, at this moment, I cannot assure reliability of a version newer than v4.038 nor answer your questions about potential errors or about the best option (timing or no-timing) to use. I'll try to keep making tests in the following weeks using Verilator v5 and let you know my findings (and, if you find anything else, please let us know).

Best regards

Dani


   
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