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Error During Verilator Sim Binary

 

arslanmajid
(@arslanmajid)
New Member
Joined: 9 months ago
Posts: 1
Topic starter  

Hello I am trying to generate Binary for simulation but getting these errors. I am using Windows and following the steps in getting started guide for verilator

/usr/local/share/verilator/include/verilated.cpp: In function ‘IData VL_FGETS_NI(std::string&, IData)’:
/usr/local/share/verilator/include/verilated.cpp:1303:36: error: ‘numeric_limits’ is not a member of ‘std’
1303 | return getLine(dest, fpi, std::numeric_limits<size_t>::max());
| ^~~~~~~~~~~~~~
/usr/local/share/verilator/include/verilated.cpp:1303:57: error: expected primary-expression before ‘>’ token
1303 | return getLine(dest, fpi, std::numeric_limits<size_t>::max());
| ^
/usr/local/share/verilator/include/verilated.cpp:1303:60: error: ‘::max’ has not been declared; did you mean ‘std::max’?
1303 | return getLine(dest, fpi, std::numeric_limits<size_t>::max());
| ^~~
| std::max
In file included from /usr/lib/gcc/x86_64-pc-cygwin/11/include/c++/algorithm:62,
from /usr/local/share/verilator/include/verilated_heavy.h:29,
from /usr/local/share/verilator/include/verilated_imp.h:29,
from /usr/local/share/verilator/include/verilated.cpp:25:
/usr/lib/gcc/x86_64-pc-cygwin/11/include/c++/bits/stl_algo.h:3467:5: note: ‘std::max’ declared here
3467 | max(initializer_list<_Tp> __l, _Compare __comp)
| ^~~
make[1]: [/usr/local/share/verilator/include/verilated.mk:241: verilated.o] Error 1
make[1]: Leaving directory '/cygdrive/E/RVfpga_Dec2021/RVfpga/verilatorSIM'
make:
[Makefile:14: Vrvfpgasim] Error 2

 


   
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dchaver
(@dchaver)
Member Moderator
Joined: 2 years ago
Posts: 50
 

Hi arslanmajid,

I think your problem is related with the versions used, both for Verilator and the packages installed in Cygwin.

Are you using RVfpga v2.2 or an older one? In Appendix C of the GSG of v2.2 we state the specific versions that must be used. 

You can also find this information in two previous posts in this forum:

  • Verilator version used in RVfpga
  • Package versions that work with RVfpga v. 2.1 on windows 10 (compile Verilator)

Let us know if you can resolve your problem or you need more help. 

Best regards

Dani


   
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