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Use Vivado to simulate the Swervolf core

 
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 Libo Chang
(@libo-chang)
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Joined: 3 years ago
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Topic starter 11/08/2022 12:01 am  
 

 

Since we need to increase the IP provided by Xilinx to  SoC based on the RISC-V , we need to simulate under Vivado. But we don't know how to store the instructions produced by the compiler.


   
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