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Help is required on adding a new peripheral to the RVFPGA SoC

 

(@fasihulhassan)
New Member
Joined: 6 months ago
Posts: 1
Topic starter  

Basically, i want to add an extra eighth pheripheral WishBone to APB bridge and connect a APB slave along with the existing 7 pheripheral on the RVFPGA  SoC. Despite my efforts, I've encountered challenges and I'm struggling to understand the intricacies. Can someone guide me where and how to make chnages. I have a fully working WB2APB bridge and it's connected to the slave. I have tested the verilog code for WB2APB bridge and it's slave standalone using vivado. It woks perfectly fine. My idea is to connect the bridge at the wb interconnect and from where signals will propagate to the apb interface and thus to the apb slave.


   
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dchaver
(@dchaver)
Member Admin
Joined: 3 years ago
Posts: 80
 

Hi fasihulhassan,

In labs 6-10 of RVfpga v2.2 ( https://university.imgtec.com/rvfpga-download-page-en/ ) we give a lot of details and exercises with solutions on how to add new peripherals. Besides, in our recently released edX course ( https://www.edx.org/es/learn/computer-programming/the-linux-foundation-computer-architecture-with-an-industrial-risc-v-core ), in Chapter 6 we explain the process to add a peripheral in more detail, so you may also find it useful.

Let me add that for the multiplexer extension you can use v1.3.0 of wb_intercon_gen2.py ( https://github.com/olofk/wb_intercon/tree/v1.3.0 ) by running:

python sw/wb_intercon_gen2.py config.yml

with a config.yml that, for example, looks like this:

files_root: .
vlnv: ::wb_intercon:0
parameters:
  masters:
    io:
      slaves : [rom, sys, spi_flash, uart]
  slaves:
    rom:
      offset : 0x00000000
      size   : 0x00001000
    sys:
      offset : 0x00001000
      size   : 0x00000040
    spi_flash:
      offset : 0x00001040
      size   : 0x00000040
    uart:
      offset : 0x00002000
      size   : 0x00001000
 
Note that you can change the config to have the number of peripherals and their mapping as you want.
 
Note also that you have to modify one line in file "wb_intercon_gen2.py" to make it work:

Line 126: 

print("Wishbone Data Resizer Endian: {}".format(config['endian']))
 
Change to:

print("Wishbone Data Resizer Endian: {}".format(self.endian))
 
Let us know if you can resolve your problems with this guidance. If you need more help, please provide us more details about your environment (OS used, RVfpga package used...) and the specific problems that you are having.
 
Best regards
Dani
 
This post was modified 6 months ago by dchaver

   
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