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Adding VGA and a frame buffer

 

(@bcruiksh)
Active Member
Joined: 4 years ago
Posts: 2
Topic starter  

Hello,

 

As part of our curriculum, I really like adding VGA capability to the RVfpga design.  I do have this working and students really enjoy it.  I want to be able to have the Swerv processor able to read and write the VGA frame buffer if possible instead of just controlling the VGA indirectly.  Maybe make the framebuffer at 0x8008_0000 and 640x480x8bits.

I have found ways to get this going a bit, by modifying some extra RTL files for a test register:

axi_intercon.sv needs to have the end_addr changed to something like 32h8010_0000

Connect frame buffer in Wishbone mux like usual. Maybe 32'h0008_0000 start with a mask of 32'hfff8_0000 inside wb_intercon.v
Change the .AW(16) to .AW(20) for the axi2wb instantiation parameter for the bus width. And change these four lines as well to expand to bit 19:
- wb_adr wire to wire [19:2] wb_adr;
- assign wb_m2s_io_adr = {12'd0,wb_adr,2'b00};
- .i_awaddr (io_awaddr[19:0]),
- .i_araddr (io_araddr[19:0]),

With all this, I have things working pretty well, but the 0x8008_0000 address seems to be cached by Lsu when I look at the verilator trace.  If I read the 0x8008_0000 address twice or more times at the same location, only the first is read.  If I access 0x8008_0008 then 0x8008_0000, then the 0x8008_0000 is read again.

Is there something that needs to be changed in the Swerv configuation to indicate to not cache this area?

If anybody wants this information on adding a VGA code, let me know.

Thanks,
Brian Cruikshank
Portland State University
ECE540 SOC FPGA design


   
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dchaver
(@dchaver)
Member Admin
Joined: 4 years ago
Posts: 92
 

Hello Brian,

There is a way in software for configuring if a memory region is cacheable or not. See sections 2.2, 2.4, 2.8.1 and 8.2.2 of the document for the SweRV EH1 available at: https://github.com /chipsalliance/Cores-SweRV/blob/master/docs/RISC-V_SweRV_EH1_PRM.pdf (link no longer working)

Our startup.S file configures the memory regions as follows:

   #cache configuration
   li t1, 0x55555555
   csrw 0x7c0, t1
 
You can use the same instructions for changing the configuration as desired.
 
Your VGA capability is something very appealing that, if possible, I'd like to be able to test.
 
Best regards
Dani
 
 

   
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