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RVfpga: How does PlatformIO call the different tools (and with what parameters)

 

ignacio.garcia
(@ignacio-garcia)
Active Member
Joined: 5 months ago
Posts: 2
Topic starter  

Hello, all.

The "abstraction layer" that the PlatformIO extension for VSCode puts over the tools that are invoked underneath when the different "Project tasks" are performed, has me a little confused. For example, I don't know where does PlatformIO get the parameters with which it calls these tools, nor do I see the invocation command line in the messages window.

More specifically, in the example on pages 13 to 15 of the Workshop Guide (in which the AL_Operations program is tested with the Vrvfpgasim simulator produced by Verilator, to generate a trace), when you press the "Generate trace" project task in PlatformIO, how does Vrvfpgasim know how long it has to run?

Digging in the "verilatorSIM" directory there is a tb.cpp file that I understand is the Test Bench that drives the simulator; which essentially is a loop that runs until the current time equals a timeout or the simulator terminates (Verilated::gotFinish()). Since the example I'm running, AL_Operations, never finishes, I assume it will end by timeout, and from the code it looks like this timeout should come as a parameter. But I don't see where the timeout is set, or how PlatformIO uses it to invoke the executable (all it says is "Generating trace from Verilator" and you don't see the command line).

Maybe I'm asking a stupid question and I just don't know enough about PlatformIO or Verilator, but could someone give me some clue?

Best regards and thank you very much!


   
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dchaver
(@dchaver)
Member Moderator
Joined: 2 years ago
Posts: 50
 

Hi Nacho,

I understand your doubts and you are not the first one to ask us this kind of questions about what is going on under the IDE. So it's not a stupid question at all, but an interesting one.

When you install PlatformIO and the ChipsAlliance platform, a folder called .platformio gets created at the home directory, which contains everything related with the IDE. In particular:

  • Inside the packages directory, you can find OpenOCD, the RISC-V toolchain, the Verilator and Whisper simulators, the WD PSP and BSP, etc.
  • Inside the platforms directory, you can find the ChipsAlliance platform (chipsalliance directory) that we use for running our RVfpga system. Among other things, this directory includes all the scripts used by PlatformIO for configuring and running RVfpga, such as platform.py, builder/main.py, builder/frameworks/wd-riscv-sdk.py, etc. You can analyze these scripts in order to understand the low-level details of PlatformIO. Specifically, script .platformio/platforms/chipsalliance/builder/main.py contains a function called "run_verilator" that establishes how the invocation of Verilator is done. Note that parameter timeout is not initialized, so it is not used in the loop implemented in tb.cpp that you were mentioning (you could easily include this parameter in the script, adding line: "+timeout=100",). So, in our case, what determines how long the simulation runs is command "time.sleep(3)" in the main.py script. You can increase/decrease the number of seconds and obtain a longer/shorter waveform.

This should resolve your questions. Besides, you may also find it useful to look up Appendix A of the Getting Started Guide, which includes instructions about how to perform each of the options available in RVfpga in command-line: program the board, compile a program, debug or run a program on the board, simulate in Verilator or Whisper, etc.

Let us know if this information helps you resolve your doubts or you need more help.

Best regards

Dani


   
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ignacio.garcia
(@ignacio-garcia)
Active Member
Joined: 5 months ago
Posts: 2
Topic starter  

@dchaver a very thorough answer, thanks a lot! I'll look into it and see if I'm able to understand how everything works this time 🙂

Best regards,

Nacho


   
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