Disassembler And Wrong Program Counter

Hi @hachat,

The SweRV EH1 processor includes the RISC-V Compressed Extension ( https://riscv.org/wp-content/uploads/2015/11/riscv-compressed-spec-v1.9.pdf). In this program you can find a mix of compressed (16-bit)
and 32-bit instructions (note that not all instructions have a compressed version and that the compressed extension allows 16-bit instructions to be freely intermixed with 32-bit instructions). By default, compressed instructions are enabled in RVfpga; if you want to disable their use, you can follow the steps described in Section 2.B of the RVfpga/Labs/Lab11/RVfpga_SweRVref document (you can find an example of a program that disables the use of compressed instructions at: RVfpga/Labs/Lab11/ExampleProgram). In SweRV EH1 the Align Stage translates the compressed instructions into the corresponding 32-bit version before providing them to the Decode Stage (you can find more explanations in Lab 11). It can be useful for you to perform the Verilator Simulation of the AL_Operations program, shown in Section 7 of the GSG (note that in the simulation the instructions are shown in the Decode Stage, where they have already been translated into the 32-bit version).

If you have more questions. please let us know.

Best regards

Dani

@dchaver 

Great! Thank you very much Dani.  Its very clear now, and learned a lot right there! That was really helpful and informative.

Best Regards,

Chathuranga