Hi,
The RISC-V Disassembly is wrong for the AL_Operations.S
It disassembles to machine codes of either 16bits or 32bits and it is not correct. (See attached image)
00000090 <main>:
90: 4e01 li t3,0
00000092 <REPEAT>:
92: 0e19 addi t3,t3,6
94: 1e7d addi t3,t3,-1
96: 003e7e13 andi t3,t3,3
9a: fe000ce3 beqz zero,92 <REPEAT>
9e: 0001 nop
As a result, the Program Counter is also showing incorrect values. ex: It goes as 90 -> 92 -> 94 -> 9a and back to Repeat at 92. But
Now I am wondering the debugging is trustworthy at all?
The correct disassembly should be:
0x00000E13
0x006E0E13
0xFFFE0E13
0x003E7E13
0xFE000AE3
0x00000013
Is there any solution?
Thank you and best regards,
Hi @hachat,
The SweRV EH1 processor includes the RISC-V Compressed Extension ( https://riscv.org/wp-content/uploads/2015/11/riscv-compressed-spec-v1.9.pdf). In this program you can find a mix of compressed (16-bit)
and 32-bit instructions (note that not all instructions have a compressed version and that the compressed extension allows 16-bit instructions to be freely intermixed with 32-bit instructions). By default, compressed instructions are enabled in RVfpga; if you want to disable their use, you can follow the steps described in Section 2.B of the RVfpga/Labs/Lab11/RVfpga_SweRVref document (you can find an example of a program that disables the use of compressed instructions at: RVfpga/Labs/Lab11/ExampleProgram). In SweRV EH1 the Align Stage translates the compressed instructions into the corresponding 32-bit version before providing them to the Decode Stage (you can find more explanations in Lab 11). It can be useful for you to perform the Verilator Simulation of the AL_Operations program, shown in Section 7 of the GSG (note that in the simulation the instructions are shown in the Decode Stage, where they have already been translated into the 32-bit version).
If you have more questions. please let us know.
Best regards
Dani
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