RVfpga: Understanding Computer Architecture & Introduction to SoC

RVfpga: Understanding Computer Architecture v1.0 in Simplified Chinese & Traditional Chinese have been updated!

First post and replies  | Last post by Jingyang Liu, 4 years ago

Errors occur when I try to generate Vrvfpgasim.(GSG,chapter 7)

First post and replies  | Last post by Theyuexia, 4 years ago

Lab 1 error with Vivado 2021.1 on Manjaro

First post and replies  | Last post by JiaChen, 4 years ago

Anyone compile SweRvolfSoC with verilator on MAC to get Vrvfpgasim successufully?

First post and replies  | Last post by guanyang.he, 4 years ago

The problem occurred after changing to another same nexys a7 development board

First post and replies  | Last post by dchaver, 4 years ago

a questionabout using the time.h library to get the execution time of the oftware program

First post and replies  | Last post by dchaver, 4 years ago

How to add user-defined instructions to the SweRV kernel ?

First post and replies  | Last post by RCWO, 4 years ago

Suggestions on Learning Verilator and Replacing simulator from Xsim to VCS

First post and replies  | Last post by guanyang.he, 4 years ago

Error implementing after adding the I2C module to SweRVolfSoC

First post and replies  | Last post by guanyang.he, 4 years ago

problem about how to modify the simulation time of verilator

First post and replies  | Last post by dchaver, 4 years ago