How do I use RISC-V FPGA in the other board instead "Nexys A7" board?

Dear Taeyong.
The ZCU-106 is a very big and expensive board. I'm sure it has more than enough capacity to run RVfpga.
The main challenges in using other boards are firstly checking there is enough space, then secondly developing the "wrappers" that map the ports on the processor to the IO on the new FPGA board. If you are a beginner, this is difficult to do. Experienced FPGA users can surely do it.

  
We are busy finishing the new labs for RVfpga v2.0 so developing for other platforms is not something we can do for you. We are thinking about offering a Basys-3 solution next year, but this is a smaller (and lower-cost) platform. We won't be touching the high-end platforms. The $199 (Academic Price) for Nexys A7 is our highest level offer.
We recommend you discuss this project with your digital design class teacher.
 
There will be a virtual solution for online learning next year - using an on-screen "Virtual Development Board" - it will look like a Nexys A7 but be entirely on-screen, not physical.
 

We are sorry that we cannot be more help at this stage.

@rcwo Greetings. I'm learning RISC-V and I have a basys 3 FPGA. I want to know if its posible to run the SwerVolf core in my fpga and if it's not posible, What other options can you suggest me about RISC-V cores in my fpga?. Thanks for reading and I hope you can answer my question. 

@richard-alexander-5 
The current configurations of the SweRV EH1 are too big for a Basys 3. 
There is a smaller version of the SweRV family (EL2), and our programme of work for next year includes porting some examples to the Basys3 board.
In the meantime I suggest you hunt for a second-hand Nexys4 DDR board - there are lots of them around (the Nexys4 was the earlier version of Nexys A7, and supports all the RVfpga Labs.).

@rcwo Thanks for the answer. I have a spartan 6 too. Can I implement the SwerVolf core in that FPGA? 

@richard-alexander-5 It's not big enough. You need an Artix 7 100T or bigger.

Posted by: @rcwo

Dear Taeyong.
The ZCU-106 is a very big and expensive board. I'm sure it has more than enough capacity to run RVfpga.
The main challenges in using other boards are firstly checking there is enough space, then secondly developing the "wrappers" that map the ports on the processor to the IO on the new FPGA board. If you are a beginner, this is difficult to do. Experienced FPGA users can surely do it.

  
We are busy finishing the new labs for RVfpga v2.0 so developing for other platforms is not something we can do for you. We are thinking about offering a Basys-3 solution next year, but this is a smaller (and lower-cost) platform. We won't be touching the high-end platforms. The $199 (Academic Price) for Nexys A7 is our highest level offer.
We recommend you discuss this project with your digital design class teacher.
 
There will be a virtual solution for online learning next year - using an on-screen "Virtual Development Board" - it will look like a Nexys A7 but be entirely on-screen, not physical.
 

We are sorry that we cannot be more help at this stage.

Dear rcwo.

I use the NEXYS4(WITHOUT DDR)  instead NEXYS A7 and changed the "wrappers",use the axi_mem_wrapper module instead  litedram_top module, also changed the rvfpga.xdc file .  vivado can generate bitstream file. The bitstream is working,but when i run VectorSorting_C-Lang example follow the RVfpga_GettingStartedGuide.pdf, the softwave is not work, the DEBUG CONSOLE output see Attach file.

It‘s great to hear your advice.

Hi @matttttt,

- In RVfpga v1.1, the VectorSorting_C-Lang example is wrong. Specifically, the src/VectorSorting_C-Lang.c file contains a program which we used for testing a question from a user in another forum post and we incorrectly released that code in RVfpga v1.1. Are you using RVfpga v1.1? In RVfpga v2.0 we have fixed that problem in the Vector Sorting example. So you can find the correct Vector Sorting program in RVfpga v2.0 and also attached to this post. Have you tested other examples in your Nexys 4? Are they also wrong?

- In case your problem is not due to the incorrect Vector Sorting source, I'd need more details. Could you share your modified SoC so that I can check it and also test it in my Nexys 4?

Thanks

Daniel

hi.@dchaver 

我使用的是RVfpga1.0。
我测试了其他的例子，它们和VectorSorting_C-Lang历程是同样的错误。

我修改了rvfpga.sv和rvfpga.xdc两个文件，附件是我修改后的文件。

I am using RVfpga1.0.
I tested other examples and they are the same error as VectorSorting_C-Lang process.

I modified the two files rvfpga.sv and rvfpga.xdc, and the attachment is my modified file.

@matttttt , I cannot find any attachment in your post.

@dchaver 

我重新上传附件总是失败，这是什么原因啊？

Hi @matttttt,

I've been doing several tests. I think that the problem may be related with the memory wrapper. Please try the rvfpganexys.sv file that I'm providing in the following zip file, which uses a different module called axi_mem. Note that you have to add two files to your SoC, called axi2mem.sv and axi_mem.v, which are also included in the zip file.

https://drive.google.com/file/d/1PEEdaMUMWXFLf7mxrIqHcBrBDNsPRQLY/view?usp=sharing

Let me know if this solves the problem.

Best regards

Daniel

hi.@dchaver 

I can't open the website, can you send the zip file to my email? (email:[email protected])

Thanks a lot.

Hi.@dchaver 

可以正常工作了。 🤗 

非常感谢。

It works.

Thanks.

Can I use the digilent genesys2 FPGA board to complete the course experiments? It seems to be an advanced version of the Nexys series FPGA board.